Thank you for the post! What do you think of other compilers, like Clash? https://clash-lang.org/ Does it make sense to compile high-level code written in languages like Haskell for FPGAs, or there are too many performance ‘traps‘ that it doesn’t work well?
No HLS tool really beats a good human designer in terms of performance for complex circuits right now, but they may offer other advantages. Clash in particular is great for security applications, because Haskell is easier to formally verify!
Makes sense :) What is the performance gap, roughly? Is it order(s) of magnitude or more like tens of percents? I have very little knowledge about FPGAs, but find it quite interesting.
It depends on the block you're designing, but it's usually between 1.1x and 2x worse for HLS tools. They're useful for R&D and for rapid prototyping, but when customers are buying based on performance, HLS-designed chips can't keep up.
This is a bit old but for DSP like subsystems on modern SoCs , Catapult HLS is used by teams to write higher quality RTL. HLS works but you need the HLS user to have intuition behind RTL.
Hey Zack, I do see potential in using LLMs as copilots, particularly in areas like verification, where there’s a significant talent bottleneck. Automating tedious verification processes or assisting with documentation and debugging could free up engineers to focus on innovation. However, for LLMs to make a substantial impact in chip verification, they would need to move beyond general-purpose reasoning and incorporate formal models to truly "understand" chip specifications. It seems to me that the key for LLMs in this field isn’t to replace engineers but to augment their efficiency in specific, well-defined areas.
Zach - do you see breakthroughs in hardware design once we take into account of reinforcement learning beyond the LLMs come into play? Or multi-agentic AI systems?
Thank you for the post! What do you think of other compilers, like Clash? https://clash-lang.org/ Does it make sense to compile high-level code written in languages like Haskell for FPGAs, or there are too many performance ‘traps‘ that it doesn’t work well?
No HLS tool really beats a good human designer in terms of performance for complex circuits right now, but they may offer other advantages. Clash in particular is great for security applications, because Haskell is easier to formally verify!
Makes sense :) What is the performance gap, roughly? Is it order(s) of magnitude or more like tens of percents? I have very little knowledge about FPGAs, but find it quite interesting.
It depends on the block you're designing, but it's usually between 1.1x and 2x worse for HLS tools. They're useful for R&D and for rapid prototyping, but when customers are buying based on performance, HLS-designed chips can't keep up.
This is a bit old but for DSP like subsystems on modern SoCs , Catapult HLS is used by teams to write higher quality RTL. HLS works but you need the HLS user to have intuition behind RTL.
Hey Zack, I do see potential in using LLMs as copilots, particularly in areas like verification, where there’s a significant talent bottleneck. Automating tedious verification processes or assisting with documentation and debugging could free up engineers to focus on innovation. However, for LLMs to make a substantial impact in chip verification, they would need to move beyond general-purpose reasoning and incorporate formal models to truly "understand" chip specifications. It seems to me that the key for LLMs in this field isn’t to replace engineers but to augment their efficiency in specific, well-defined areas.
Zach - do you see breakthroughs in hardware design once we take into account of reinforcement learning beyond the LLMs come into play? Or multi-agentic AI systems?