# The Future of Analog Circuit Design is Pseudo-Digital

### An emerging technique for deep submicron analog design.

TSMC recently announced that they hope to ship their first 1.6nm process technology by 2026. While that number is basically meaningless these days — no physical dimension on those upcoming TSMC chips is actually going to be 1.6nm long — it does represent a major increase in transistor density, which means we’ll be able to get more computing power out of even smaller chips. Everybody is very excited, except for maybe the analog designers. Because designing analog circuits using these cutting edge process nodes is really, really hard.

The two biggest challenges in analog circuit design are wire resistance1 and transistor variability. As you shrink your process node, wires get narrower, and their resistance increases. That means it's harder and harder to design analog circuits without unwanted resistance between any two points. And as transistors get smaller, they get harder and harder to build exactly as the designer specified. In a modern process node, key transistor parameters like threshold voltage can vary wildly from chip to chip, which makes designing an analog circuit that works consistently across multiple chips a major challenge.

So how do you design an analog circuit in a modern process node without these effects ruining your design’s performance and reliability?

# Analog Design in Modern Process Nodes

I’ve designed analog circuits in 7nm and 5nm FinFET process nodes, and in those extremely small process nodes, designers have to leverage new kinds of circuits to achieve good performance. I think the most exciting new technique is pseudo-digital design. Pseudo-digital design is a method to design analog circuits that look a lot more like digital ones: they have many more transistors that are much smaller, and often leverage the analog properties of digital logic gates.

Pseudo-digital circuits are usually easier to design, because large portions of the circuit can be synthesized using digital design tools, rather than manually drawn by an analog designer. And they manage to side-step many of the challenges faced by analog designers in modern process nodes: most notably, wire resistance and transistor variability. Often, pseudo-digital circuits aren’t even designed to minimize these effects! Instead, they leverage calibration algorithms to achieve good performance regardless. In modern process nodes, adding a few thousand logic gates to implement a calibration scheme is usually smaller and more power-efficient than designing large, interleaved, and carefully matched analog circuits that inherently avoid variability or wire resistance.

One of my favorite examples of a pseudo-digital circuit is the stochastic analog-to-digital converter, or stochastic ADC. It’s an incredibly simple way to use digital gates to perform analog-to-digital conversion, which usually requires analog components. To understand the stochastic ADC, though, we first need to understand the traditional ADC it’s descended from: the flash ADC.

# Background: Flash ADCs

What is an analog-to-digital converter in the first place? Simply put, an ADC takes an analog input signal and converts it into a digital code. If you build a 4-bit ADC with an input range of 0V to 1V, the analog input of 0V would result in a code of 0000, while the analog input of 1V would result in a code of 1111, representing 15. An analog input of 0.5V would result in a code of 0111, representing 7.

The flash ADC is one of the simplest forms of analog-to-digital converters out there. It’s the first architecture discussed in most courses on analog-to-digital converters, because it’s one of the easiest to understand and explain. Essentially, the flash ADC generates a number of reference voltages, and uses a circuit called a **comparator** to compare the input signal to each of those reference voltages. Then, it sums up the total number of comparator outputs to generate a binary output code.

The two main analog components of the flash ADC are the reference voltages, and the comparators, and each of them pose a challenge in modern process nodes. Normally, reference voltages are generated using a large number of resistors, each with the same value. However, resistors are generally large, and it’s difficult to ensure they all have the same value. Some designs leverage switched capacitors to generate their reference voltages, but often face similar problems. Ultimately, generating a large number of equally-spaced reference voltages is difficult when individual components have high variability.

The comparators themselves also pose a challenge to designers. The goal of a comparator is simple: it compares two input signals, and outputs a 1 or a 0 based on which value is larger. The classic implementation is the StrongArm latch:

The StrongARM latch has an issue as it scales to more modern process nodes, though: offset. Our ideal comparator will output a **1** if **Vin1 > Vin2**, and a **0** otherwise. But if the M1-M2 or M3-M4 transistor pairs are poorly matched, the comparator might output a **1** if **Vin > Vin2 + 50mV** instead.

There are a handful of possible solutions, but all of them come at a cost. Increasing the overall transistor size makes them easier to manufacture accurately and reduces mismatch, but makes the comparator larger and more power-hungry. More complex circuit topologies may also reduce mismatch or increase performance. Double-tailed comparators reduce power consumption at the cost of area, while auto-zeroed comparators reduce offset at the cost of power consumption. Regardless, there’s no free lunch; if you want a comparator that’s highly accurate, you need to sacrifice area or power to get it. And in modern process nodes, those tradeoffs become even more difficult to make.

Luckily, there may be a better way. Instead of spending lots of effort carefully designing a circuit to minimize the effects of mismatch, we could instead embrace that mismatch. That’s how we end up with the stochastic ADC.

# The Stochastic ADC

Stochastic ADCs work similarly to flash ADCs, in that they have many different comparators checking the input signal at once. However, the stochastic ADC is entirely made up of digital gates, so we’re unable to build large, accurate comparators, or even to generate reference voltages to compare to! Instead, the stochastic ADC leverages the variability of small transistors to its advantage.

The stochastic ADC takes two analog inputs and sends them to the input of a large number of extremely simple comparators. Each comparator consists of two cross-coupled NAND3 standard cells, with no custom analog design to speak of. There’s no reference voltage used by any of the comparators, just two inputs, **in+** and **in-**, and a clock signal **Φ**.

Because NAND3 gates are so small — they often use the smallest transistor allowed by the chip fab — there’s a lot of random variability between the different gates. One comparator might be perfectly matched, and output a **1** when **in+ > in-** and a **0** when **in- > in+**. Another comparator might have an offset of **50mV**, so it only outputs a **1** when **in+ > in- + 50mV**, and a **0** otherwise. But while this was a problem for a normal ADC, it’s actually beneficial for the stochastic ADC.

When you build hundreds of these little comparators, each with their own random offset, you’ll end up with a set of comparator offsets that are approximately normally distributed. So, if you vary the differential input signal, and count up the total number of comparators outputting a 1, you’d generate the **Raw Gaussian Data** plot on the left.

The stochastic ADC avoids investing the time and effort to design a highly linear set of reference voltages for the comparators’ inputs. Instead, it uses a calibration algorithm to linearize *outputs* from the comparators, and go from a Gaussian distribution to a linear function. In a modern process node, where digital logic is cheap and large, linear analog circuits are expensive, this gives the stochastic ADC an advantage over its flash ADC counterpart. Weaver et. al. choose to build a digital circuit to automatically perform this linearization, but you could just as easily save the gates and do that in software.

What’s exciting about the stochastic ADC is that it requires no analog design at all! All of the gates can be automatically placed by a digital synthesis tool. And as processes nodes get smaller, tiny transistors with high variability don’t pose the same challenges to stochastic ADCs as they do to flash ADCs; as a matter of fact, they may even make stochastic ADCs better!

# Pseudo-Digital Design in Practice

The stochastic ADC is a really great example to help understand the basics of pseudo-digital design, but it’s not necessarily the most practical design to use in actual production silicon -- it’s fairly large and burns a lot of power for a fairly simple function that isn’t required by a lot of chips in modern process nodes. But now that you understand some of the key concepts behind pseudo-digital design, some of these more practical designs might pique your interest.

The edge-pursuit comparator is a comparator that uses ring oscillators to compare voltages in a power-efficient way.

An all-digital temperature sensor can be constructed out of ring oscillators operating at different supply voltages. A similar sensor can be constructed by charging and discharging the gate capacitance of a standard cell.

All-digital phase-locked-loops leverage digital phase comparison and time-to-digital conversion, rather than analog voltage-controlled oscillators. They’re even available commercially.

A high-speed IO link can leverage synthesized, all-digital duty-cycle calibration.

Overall, I see pseudo-digital analog design as an incredibly promising way to develop analog circuits that work well even as process nodes continue scaling to 1.6nm and beyond.

Also capacitance, but I’m simplifying a bit here for non-EEs.