While I fundamentally agree, my understanding is that companies like Synopsys primarily bundle their IP offerings along with EDA tools - so a lot of big players already have access to these IP.
I'm curious to hear what specific IPs you think could be useful today that aren't available, and can also take a performance hit?
Good question, and this is definitely a challenge! If AI-powered tools let you offer IP at a reduced price, that could definitely help you overcome some of the inertia that existing IP providers get due to bundling.
At the same time, IP for emerging standards is a place where I think there's opportunity to replace conventional vendors. If AI-powered tools let you be first to market with DDR6 memory controller IP, or CXL controller IP, or ML-KEM cryptography IP, that's a prime way to disrupt existing IP providers.
Great to get your insight about chip designs and where LLM-based design can actually live up to the hype.
Somewhat tangential to the post, what do you think of iteratively designing chips using FPGA's and LLM written Verilog? It seems more feasible for LLM's to write verilog given feedback and toy examples of human engineers working through design problems.
Mohamed S. Abdelfattah talks about co-design on FPGA's (without LLM's) here:
I'm a big advocate of co-design and iterative design! I don't even think it needs to necessarily be done on FPGAs -- with good simulation and modelling tools, you can iteratively co-design ASICs too :)
This is an interesting take, thanks for sharing!
While I fundamentally agree, my understanding is that companies like Synopsys primarily bundle their IP offerings along with EDA tools - so a lot of big players already have access to these IP.
I'm curious to hear what specific IPs you think could be useful today that aren't available, and can also take a performance hit?
Good question, and this is definitely a challenge! If AI-powered tools let you offer IP at a reduced price, that could definitely help you overcome some of the inertia that existing IP providers get due to bundling.
At the same time, IP for emerging standards is a place where I think there's opportunity to replace conventional vendors. If AI-powered tools let you be first to market with DDR6 memory controller IP, or CXL controller IP, or ML-KEM cryptography IP, that's a prime way to disrupt existing IP providers.
There is another avenue for AI-based EDA startups: get acquired by Cadence / Synopsys for a sizable few million and call it a day.
Big companies are eager for AI to replace engineers whether it can happen or not. Payroll is $$, and AI that works can minimize headcount.
The AI hype cycle is the best window for startups to make this happen. Hence the startup boom.
Great to get your insight about chip designs and where LLM-based design can actually live up to the hype.
Somewhat tangential to the post, what do you think of iteratively designing chips using FPGA's and LLM written Verilog? It seems more feasible for LLM's to write verilog given feedback and toy examples of human engineers working through design problems.
Mohamed S. Abdelfattah talks about co-design on FPGA's (without LLM's) here:
https://youtu.be/WWCWsub3YkE?t=1737
I'm a big advocate of co-design and iterative design! I don't even think it needs to necessarily be done on FPGAs -- with good simulation and modelling tools, you can iteratively co-design ASICs too :)
This is definitely a space worth looking into.