Why is it so hard for startups to compete with Cadence?

And is Morris Chang’s daughter single?

If you talk to any chip designer, they’ll complain about Cadence’s chip design software. They’ll probably complain about Synopsys too, and maybe Mentor Graphics (which is now owned by Siemens, but everybody still calls them Mentor Graphics). These three companies have an oligopoly on chip design software, despite their software being slow, difficult to use, segfaulting constantly, and having user interfaces that look like they were designed in 2003. But if everybody hates these electronic design automation (EDA) tools so much, why hasn’t a cool new startup disrupted the industry?

Well, startups have been trying for years. Way back in 2007, Xoomsys developed parallel Spice simulators to greatly speed up analog and mixed signal simulators, but failed to ever reach mainstream adoption. In 2011, Extreme DA was acquired by Synopsys for their multi-core static timing analysis tools. Rocketick Technologies met a similar fate in 2016, being acquired by Cadence for their multi-core RTL simulator. And in 2025, Partcl is building GPU accelerated chip placement and signoff tools.

In the past, all of these startups either failed or got acquired for $100-500M by the big players like Cadence or Synopsys, and folded into their product portfolio. None of them grew to the size and scale where they could actually break up the Cadence-Synopsys-Mentor oligopoly. The biggest culprit has nothing to do with technology, and everything to do with the unique relationship Cadence, Synopsys, and Mentor have with bleeding-edge fabs like TSMC and Samsung.

The EDA Alliance Axis

TSMC is probably the most important fab in the world. The most valuable chips, from Apple’s M4 CPUs to NVidia B200 GPUs, are made in their foundries in Taiwan. And TSMC maintains close relationships with a small number of EDA vendors, dubbed the “EDA Alliance”. Some of these vendors have their tools officially certified to work with TSMC processes. For example, here are the certifications for TSMC’s 3nm process:

Even the third largest EDA vendor in the world, Siemens, doesn’t have complete certification coverage! It’s incredibly hard for a startup to get a single tool qualified, let alone multiple. And when chip designers working in modern process nodes spend millions of dollars on mask sets and manufacturing runs, they are very unlikely to take a risk on a tool that isn’t officially certified and supported by TSMC.

TSMC is a huge company, without a major incentive to work with startups to certify their tools. When people ask me about competing with Cadence, my tongue-in-cheek response would be that the best first step would be to marry one of the daughters of Morris Chang, TSMC’s legendary founder. It’s a joke, but it rings a bit true -- to make waves in the EDA industry, you need your tools to get certified, and for that, you need to somehow curry favor with TSMC.

This problem is exacerbated by the sheer complexity of modern process nodes. Building static timing analysis tools for the 28nm process node back in 2010 was much, much easier than building the same tool for the modern 2nm process. Modern tools need massive parallelism to fit large designs, and require complex features to incorporate effects of local statistical variation on the behavior of every individual transistor in the design. It’s simply a lot harder to build a good tool to support a modern process node.

Some tools developed by startups have had some success though! How did they pull it off? And more importantly, how can new startups replicate that same success?

The Startup Rebels

If developing a fully certified and qualified tool as a startup is so hard, how’s a startup to take on the EDA Alliance? Well, even if every chip designer wants their final signoff flow to rely on certified and qualified tools, that doesn’t mean that they can only use those tools.

Most larger chip companies maintain a redundant suite of EDA tools, ranging from simulators to sign-off tools. If your tool is faster, but not certified, it may find a niche in a certain part of the chip design flow. For example, an incredibly fast synthesis and timing analysis tool may enable much faster design space exploration, enabling chip designers to estimate whether their design will meet timing without having to leverage the expensive and slow but fully-qualified tools from Cadence and Synopsys.

Some companies are taking this idea even further. Silimate offers an AI-powered PPA prediction tool that can provide rough estimates of a chip’s power consumption and timing characteristics far faster than a conventional synthesis and signoff tool suite can. Obviously a prediction tool will never be qualified the same way that a signoff tool could be, but it proves the value of fast iteration times independent of signoff-ready certification. Perhaps tools like Partcl could end up in this “complimentary tools” category at first.

This strategy has two major downsides, though. The primary buyers of these sorts of tools are companies that already maintain a suite of redundant EDA tools, and those buyers are usually large companies. Chip design startups simply don’t have the budget to own multiple versions of the same tool. That means that EDA startups selling these “complimentary” tools won’t be able to reap the benefits of selling to other startups. It also could paint a target on their back that’s clearly visible to Cadence and Synopsys. There’s a reason why so many EDA startups either get acquired for less than $500M, or get sued into oblivion by major EDA companies.

Ultimately, if a startup wants to actually take down Cadence and Synopsys, they’ll need to get certified by TSMC, Samsung, GlobalFoundries, and all the other major fabs. But in the meantime, they can build market share by focusing less on replacing the existing qualified tools, but by complimenting them. And if they can withstand the IP lawsuits and enticing acquisition offers, they may even be able to meaningfully compete with the big EDA companies. And all that without marrying Morris Chang’s daughter.