Great article as usual! I'm a bit of a noob - why does synthesis take so long? And are the conventional players doing anything to speed up the process?
It's an NP-hard problem! You have to do boolean circuit optimization, while also being aware of all of the timing and power characteristics of all of the standard cells.
Existing players are trying to improve their tools all the time, but they're still just making incremental improvements on their conventional codebase, which isn't designed for high-speed parallel execution.
I was wondering about this and it's great to get a nuanced take on using LLM's for chip design.
Would FPGA's be useful for pre-training such a model? I know they're kind of a low quality way to simulate circuits, but perhaps fast and bad is sufficient for some model training?
When it comes to building high-quality data, the long time per example might not be so much of an issue. It seems like many simulations could be run in parallel and results like LIMI make me think that ~100 examples in each subdomain of circuit design might be sufficient to boost productivity:
Even FPGAs require synthesis and place-and-route steps to go from Verilog to a bitstream. Those steps are faster than they are for ASICs, but not by enough to make them viable for RL.
You could skip these steps and train your model purely based on code correctness, but without being able to analyze area, timing, and power consumption, you model won't learn to write efficient, performant Verilog.
Great article as usual! I'm a bit of a noob - why does synthesis take so long? And are the conventional players doing anything to speed up the process?
It's an NP-hard problem! You have to do boolean circuit optimization, while also being aware of all of the timing and power characteristics of all of the standard cells.
Existing players are trying to improve their tools all the time, but they're still just making incremental improvements on their conventional codebase, which isn't designed for high-speed parallel execution.
That makes sense, thank you!
I was wondering about this and it's great to get a nuanced take on using LLM's for chip design.
Would FPGA's be useful for pre-training such a model? I know they're kind of a low quality way to simulate circuits, but perhaps fast and bad is sufficient for some model training?
When it comes to building high-quality data, the long time per example might not be so much of an issue. It seems like many simulations could be run in parallel and results like LIMI make me think that ~100 examples in each subdomain of circuit design might be sufficient to boost productivity:
https://arxiv.org/abs/2509.17567
Even FPGAs require synthesis and place-and-route steps to go from Verilog to a bitstream. Those steps are faster than they are for ASICs, but not by enough to make them viable for RL.
You could skip these steps and train your model purely based on code correctness, but without being able to analyze area, timing, and power consumption, you model won't learn to write efficient, performant Verilog.
Interesting, that makes sense. I'll have to look around for efforts to accelerate the synthesis and place-and-route algorithms. Though it is NP hard.